1. Field of Invention
The present invention relates to a display device, and more particularly, to a display device including an interlayer insulating layer that may reduce parasitic capacitance.
2. Description of the Background
Generally, among flat panel displays (FPD), organic light emitting displays (OLED) have recently been spotlighted because they may be driven with low voltage, are light and thin, have a wide view angle, and respond at high speed. OLEDs may be passive matrix or active matrix according to their driving method. Passive matrix OLEDs may be manufactured through relatively simple processes, however, their power consumption may rapidly increase as display area and resolution increase. Therefore, passive matrix OLEDs are typically used as smaller displays. On the other hand, active matrix OLEDs may be manufactured through relatively complicated processes, however, they may have large screens and high resolution.
In active matrix OLEDs, thin film transistors (TFT) are included in each pixel region to control emission of the pixel's organic light emitting layer. A pixel electrode is provided in each pixel region and is electrically separated from adjacent pixel electrodes so that it may be independently driven. A wall, which is higher than the pixel electrode, is formed between pixel regions. The wall prevents pixel electrodes from shorting with each other, and it separates pixel regions from each other. A hole injecting layer and an organic light emitting layer may be sequentially formed on the pixel electrode between walls.
A plurality of transistors may be arranged in one pixel in an OLED. In general, the pixel may include a switching transistor connected to a data line and a driving transistor connected to a driving voltage line. With such a complicated structure, parasitic capacitance may be generated between wiring line layer, thereby deteriorating the display's quality.